In certain circuit applications wherein two clocks need to be tracked, a “frequency lock indicator” may be required. A frequency lock indicator may be activated when it is determined that two clock signals are the same frequency, within a certain tolerance. One example application that requires a frequency lock indicator is a phase-locked loop (PLL) application. A PLL is set up to operate in a certain frequency range and a typical PLL compares a reference clock to a feedback clock via a phase-frequency detector. If the feedback clock is, for example, too slow, the frequency of the feedback clock is increased until the two clocks are of equal phase and frequency and the PLL is considered locked. A lock indicator, such as the output of a phase-frequency detector, provides a mechanism for indicating when the PLL is locked.
A problem with, for example, current PLL lock indicators is that each PLL is designed for a certain amount of jitter tolerance for operating at high speed in the field and the sensitivity of the lock indicator is fixed accordingly. However, during, for example, manufacturing test operations, the PLL may be running at a low speed, but with the same fixed jitter sensitivity as when running at high speed and, thus, during test operations the PLL may continuously become unlocked. Therefore, during test the use of the PLL lock indicator directly may not be reliable. Consequently, it may be beneficial to develop improved methods of generating frequency lock indicators for PLL and other applications.